1. Field of the Invention
The present invention relates to charge pump circuits, and in particular, to charge pump circuits using metal oxide semiconductor field effect transistors (MOSFETs).
2. Description of the Related Art
Charge pump circuits, in general, are well known in the art. Such circuits are used when a circuit node needs to be charged to some predetermined voltage level. For example, referring to FIG. 1, one common application for charge pump circuits is a phase lock loop. In accordance with well known principles, the output signal from a voltage controlled oscillator (VCO) is divided down (in frequency) and compared against a reference oscillator signal. This comparison is done with a phase comparator, or phase detector, with the charge pump circuit being part of the phase comparator. The output from the phase comparator is filtered by a loop filter (e.g. low pass) to produce, at an output node, a dc voltage for driving the VCO.
Referring to FIG. 2, one form of conventional charge pump circuit 10 includes a "pump-up" current mirror 12 with an associated input current switch 14 and a "pump-down" current mirror 16 with an associated output current switch 18, coupled together at an output node 20. The first current mirror 12 has an input P-MOSFET 22 whose drain and gate terminals are connected to the gate terminal of an output P-MOSFET 24. The source terminals of these P-MOSFETs 22, 24 are connected to the positive supply voltage VDD. The incoming pump-up signal 15 is a positive logic binary signal which turns the N-MOSFET 14 input current switch off and on to establish an input reference current I.sub.REF1 through the input P-MOSFET 22 and current limiting resistor 26. This reference current I.sub.REF1 is replicated, or "mirrored", in the output P-MOSFET 24 to provide a pump-up current I.sub.PU.
The second current mirror 16 is the "analog" of the first current mirror 12, i.e. with N-MOSFETs and P-MOSFETs substituted for P-MOSFETs and N-MOSFETs, respectively. Accordingly, the incoming pump-down signal 19, which is a negative logic binary signal, turns the P-MOSFET 18 input current switch off and on to establish an input reference current I.sub.REF2 through the input P-MOSFET 28 and current limiting resistor 32. This reference current I.sub.REF2 is replicated in the output N-MOSFET 30 to sink a pump-down current I.sub.PD.
Frequently, it is necessary to source a relatively large pump-up current I.sub.PU and sink a relatively large pump-down current I.sub.PD to and from the output node 20, respectively. Accordingly, the output, or driver, MOSFETs 24, 30 are typically actually several MOSFETs connected in parallel with one another with each one replicating the input, or reference, current. For example, in the charge pump circuit 10 of FIG. 2, the output P-MOSFET 24 and N-MOSFET 30 each actually represent a number of such devices (e.g. 5-10 each) connected in parallel. This allows the replicating action of the current mirrors 12, 16 to also introduce multiplication factors into such current replication process.
While this type of charge pump circuit is well suited to many applications, a number of drawbacks nonetheless exist. For example, the size of the output MOSFETs 24, 30 are typically quite large due to the relatively high output current demands (e.g. sourcing and sinking) and the dynamic output voltage range. Such large devices are subject to high leakage currents due to scalable effects such as subthreshold leakage, gate induced drain-to-well leakage and parasitic Schottky diode (drain-to-well) leakage caused by shallow junctions. Such leakage effects are at best undesirable and at worst quite problematic in many applications. For example, for a phase lock loop (e.g. FIG. 1) in which the charge pump circuit 10 is to be operated in an open loop mode for any period of time, such as for open loop modulation, such leakage results in an unstable VCO tuning voltage at the output node 20. This, in turn, causes problems with respect to frequency stability at the output of the VCO in the form of unwanted frequency deviation, higher output noise levels and higher magnitude spurious signals due to the phase loop reference.
One way to reduce these leakage effects would be scale down the current mirror devices, particularly the output MOSFETs 24, 30. However, this would have the undesirable effect of increasing the effective series resistance of the MOSFET channels thereby reducing the operating range of the current mirror (e.g. useable output voltage V.sub.DS), as well as increasing the gate voltage necessary for driving the MOSFET to provide the same amount of output current. Furthermore, scaling down the devices can result in "short" MOSFET channels (e.g. less than 0.5 micron). This is undesirable due to well known problems caused by short channel effects. Therefore, it is desirable to maintain "long" MOSFET channels (e.g. approximately 2 microns). Accordingly, in order to keep the MOSFET channel resistance constant, the channel width must then also be proportionately higher, consistent with the length of the channel.
Another problem associated with this conventional charge pump circuit 10 relates to the fact that the input reference currents I.sub.REF1, I.sub.REF2 for the current mirrors 12, 16 are typically switched on only during a pump condition. Generally, the reference currents I.sub.REF1, I.sub.REF2 are kept as small as possible so as to minimize power consumption. This results in time constants at the gate terminals of the output MOSFETs 24, 30 being long due to the large dimensions of the output MOSFETs 24, 30 (as noted above). Due to such long time constants, the time required for the pump currents I.sub.PU, I.sub.PD to reach their final values, both on and off, are also long. This, in turn, can result in long pump correction times, resulting in excess accumulated charges at the output node 20, thereby causing further voltage fluctuation at the output node 20.
Accordingly, it would be desirable to have an improved charge pump circuit design which avoids the need for, and therefore the problems associated with, scaling down MOSFET device dimensions for minimizing leakage effects. It would be further desirable to have such an improved charge pump circuit design which also avoids the problems associated with long time constants associated with the pump-up and pump-down currents.